The present invention relates to a semiconductor memory device and more particularly to a method for making in the semiconductor memory device a sense amplifier that senses and amplifies data stored in a memory cell.
In a semiconductor memory device, particularly a dynamic Random Access Memory device (hereinafter, referred to as DRAM), data stored in a memory cell selected by a row decoder is charged or discharged to a bit line connected to a drain of a cell transistor, and the information appearing in a form of voltage difference on the bit line is sensed and amplified by a sense amplifier connected in parallel to the bit line and read out of the DRAM. Then, in the memory cell that has been read out, an original data is charged or discharged to maintain a dynamic memory function.
However, as the integration of memory devices increase more and more and their operation speed goes extremely higher, an electrostatic capacitance of a memory cell is reduced more, and consequently the memory cell is burdened with a load caused by the electrostatic capacitance of the bit line. For those who are skilled in the art it will be easy to recognize that the electrostatic capacitance of the memory cell should be closer to that of the bit line for a faster sensing operation.
FIG. 1 is a block diagram of a DRAM including a sense amplifier construction according to a prior art, wherein there are a plurality of memory cell arrays, each of the memory cell arrays 20, 60, 65, 25 having its own equalizing circuits 10, 70, 75, 15 and sense amplifiers 30, 50, 55, 35, respectively. There are further included transfer circuits 40, 45 to connect or separate adjacent memory cell arrays between each of the sense amplifiers 30, 50, 55, 35 connected to each of the memory cell arrays 20, 60, 65, 25.; and row decoders 90, 91, 92, 93, each connected to a word line of each of the memory cell arrays 20, 60, 65, 25. Every two memory cell arrays 20, 60, 65, 25 share one of column decoders 80, 81, 83. In this configuration of the DRAM, an input/output lines, to which data through the sense amplifiers 30, 50, 55, 35 are finally transferred, is included in the column decoder 80.
In such construction of a DRAM, assuming the position of the column decoder 80 as a center, when the left-sided external cell array 20 is selected, data is transferred through a path including sequentially, the external cell array 20, the first sense amplifier 30, the transfer circuit 40, the second sense amplifier 50, the internal cell array 60 and the input/output lines, whereas when the left-sided internal cell array 60 is selected, data is transferred through a path including the internal cell array 60, a second sense amplifier 50 and the input/output lines.
FIG. 2 shows a detailed circuit connection between the left-sided equalizing circuits 10, 70, the transfer circuit 40, the sense amplifiers 30, 50, and the left-sided external and internal memory cell arrays 20, 60 and the input/output lines.
In the circuit diagram illustrated in FIG. 2, there are shown, from the left to the right, the first equalizing circuit 10 having transistors 12-14 that receive a first equalizing signal 11 through gates; the external memory cell array 20; the first sense amplifier circuit 30 having two PMOS transistors 32, 33 whose gates are cross-coupled with external bit lines 24, 24'; the first transfer circuit 40 which connects the external bit lines 24, 24' with internal bit lines 64, 64', having two NMOS transistors 42, 43 that are used for transfer and controlled by a given separation signal 41; the second sense amplifier 50 having two NMOS transistors 52, 53 whose gates are cross-coupled with the internal memory cell array 60; the second equalizing circuit 70 having an NMOS transistor 72 that receives a second equalizing signal 71 through a gate; and the second transfer circuit 45 which connects the internal bit lines 64, 64' with input/output lines 84, 85 respectively, having two NMOS transistors 82, 83 that are used for transfer and controlled by a given separation signal 81. An equalizing voltage 9 with level of 1/2 Vcc is applied to between the NMOS transistors 12 and 14 of the first equalizing circuit 10.
The operation of the aforementioned prior art sense amplifier shall be explained hereafter, by way of an example, in a case where the external memory cell array 20 is selected in the circuit illustrated in FIG. 2. Before data is read out from a memory cell in the external memory cell array 20 having an NMOS transistor 22 and a capacitor 23, the external bit lines 24, 24' together with other bit lines are precharged and equalized at the level of 1/2 Vcc. And then, when a first word line 21 is selected, electric charges charged in the capacitor 23 is charged or discharged to the external bit line 24 through the NMOS transistor 22. Before the word line 21 is selected, an external equalizing signal 11 and the first separation signal 41 of the first transfer circuit 40 is in disabled state.
Once data is sensed and sufficiently amplified at the external bit lines 24, 24', the first separation signal 41 applied to the first transfer circuit 40 reaches "high" state and the voltage amplified on the external bit lines 24, 24' is transferred to the internal bit lines 64, 64'. Next, the voltage transferred to the internal bit lines 64, 64' goes to the input/output lines 84, 85 through the transfer transistors 82, 83 of the second transfer circuit 45.
When the voltage on the external bit lines is transferred to the internal bit lines, data is recharged in the selected memory cell of the external memory cell array 20. As stated in the foregoing description, when the word line is selected and the charges are discharged from the memory cell to bit lines, a data voltage appearing on the corresponding bit lines, because the data voltage appears dependently upon an electrostatic capacitance of the bit lines, has to exceed the electrostatic capacitance of the bit lines so that the electric potential of the bit lines can be split at the equalizing level of 1/2 Vcc to enable sensing operation.
In the configuration of the prior art, however, it takes more time for the data voltage to overcome the electrostatic capacitance of the bit lines, which then has come to be relatively higher by a reduction of electrostatic capacitance of the memory cell, i.e., the reduction of capacitance of a capacitor in the memory cell due to high integration of the memory device. As consequence, access time in reading data slows down because sensing operation of the sense amplifier circuit is delayed.